Influence of polarized bias and porous silicon morphology on the electrical behavior of Au-porous si

This paper reports the surface morphology and Ⅰ-Ⅴ curves of porous silicon (PS) samples and related devices. The observed fabrics on the PS surface were found to affect the electrical property of PS devices. When the devices were operated under different external bias (10 V or 3 V) for 10 min, their observed obvious differences in electrical properties may be due to the different control mechanisms in the Al/PS interface and PS matrix morphology.