An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement Coverage

  • 期刊名字:计算机科学技术学报(英文版)
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  • 论文作者:Wei Lu,Xiu-Tao Yang,Tao Lv,Xia
  • 作者单位:Institute of Computing Technology,Graduate School of the Chinese Academy of Sciences,School of Computer and Information
  • 更新时间:2023-04-18
  • 下载次数:
论文简介

Coverage evaluation is indispensable for verification via simulation. As the functional complexity of modern design is increasing at a breathtaking pace, it is requisite to take observability into account. Unfortunately, nowadays coverage metrics taking observability into account are not very satisfactory. On the one hand, for the observability assessment algorithms proposed up to now, the overhead of computing is large, so they could not be integrated into simulation tools easily. On the other hand, the vector generation methods involving the metrics taking observability into account are not very efficient, and there exists a disconnection between these metrics and the vector generation process.In this paper, some original ideas for the problems above are presented. (1) Precise and concise abstract representations from HDL (Hardware Description Language) descriptions at RTL (Register Transfer Level) are presented to model observability information. (2) A novel observability evaluation method based on the proposed models is introduced. This method is more computationally efficient than prior efforts to assess observability and it could be integrated into compilers and simulators easily. (3) A new simulation vector generation procedure involving the observability-enhanced statement coverage metric is developed. The method is simulation-based and driven by the distribution of unobserved statements.During this procedure, the proposed algorithm always tries to cover all unobserved statements, and reduce unnecessary backtracking, so it is efficient. The methods proposed have been implemented as a prototype tool for VHDL designs, and the results on benchmarks show significant benefits.

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